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M36L0R7060U1 M36L0R7060L1 M36L0R7050U1 M36L0R7050L1
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package
Preliminary Data
Feature summary
Multi-Chip Package - 1 die of 128 Mbit (8Mb x16, Mux I/O Multiple Bank, Multi-level, Burst) Flash Memory - 1 die of 32 or 64Mbit Mux I/O, Burst Pseudo SRAM Supply voltage - VDDF = VDDP = VDDQF = 1.7 to 1.95V - VPPF = 9V for fast program Electronic signature - Manufacturer Code: 20h - Device Codes (Top Flash Configuration): M36L0R7060U1: 882Eh, M36L0R7050U1: 882Eh - Device Codes (Bottom Flash Configuration) M36L0R7060L1: 882Fh M36L0R7050L1: 882Fh ECOPACK(R) package
FBGA
TFBGA88 (ZAM) 8 x 10mm
Dual operations - program/erase in one Bank while read in others - No delay between Read and Write operations Block locking - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WPF for Block Lock-Down - Absolute Write Protection with VPPF = VSS Common Flash Interface (CFI)
Flash memory

Multiplexed address/data Synchronous / asynchronous read - Synchronous Burst Read mode: 66MHz - Random Access: 85ns Synchronous burst read suspend programming time - 10s typical Word program time using Buffer Enhanced Factory Program command Memory organization - Multiple Bank Memory Array: 8 Mbit Banks - Parameter Blocks (Top or Bottom location) Security - 64 bit unique device number - 2112 bit user programmable OTP Cells 100,000 program/erase cycles per block

PSRAM
Access time: 70ns Synchronous modes: - Synchronous Write: continuous burst - Synchronous Read: continuous burst or fixed length: 4, 8 or 16 Words for 32 Mbit devices or 4, 8,16 or 32 Words for 64 Mbit devices - Maximum Clock Frequency: 83MHz Low power consumption Low power features - Partial Array Self-Refresh (PASR) - Deep Power-Down (DPD) Mode - Automatic Temperature-compensated SelfRefresh

June 2006
Rev 1
1/22
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 Address Inputs (ADQ0-ADQ15 and A16-A22) . . . . . . . . . . . . . . . . . . . . . 10 Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash memory Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash memory Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Chip Enable (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 12 VDDF Flash memory Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCCP PSRAM Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDDQF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPPF Flash memory Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . 13 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 4 5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Contents
6 7 8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating modes - Standard Asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stacked TFBGA88 8 x 10mm - 8 x 10 active ball array, 0.8mm pitch, package data . . . . 19 Part numbering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TFBGA88 8 x 10mm, 8 x 10 ball array - 0.8mm pitch, bottom view package outline. . . . . 19
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Summary description
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
1
Summary description
The M36L0R7060U1, M36L0R7060L1, M36L0R7050U1 and M36L0R7050L1 combine two memory devices in a Multi-Chip Package:

a 128-Mbit, Multiple Bank Flash memory, the M58LR128G(U/L) a 32 or 64 Mbit PseudoSRAM, the M69KM048AA or M69KM096AA, respectively.
The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58LRxxxGUL and M69KM048AA or M69KM096AA datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the STMicroelectronics website: www.st.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 x10mm, 8 x 10 ball array, 0.8mm pitch) package. In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
6/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Figure 1. Logic diagram
VDDQF VDDF 23 A16-A22 VPPF VDDP 16
Summary description
ADQ0-ADQ15 EF GF WF RPF WPF L K EP GP WP CRP UBP LBP M36L0R7060U1 M36L0R7060L1 M36L0R7050U1 M36L0R7050L1 WAIT
VSS
Ai12016
7/22
Summary description Table 1.
A16-A22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Signal names
(1), (2)
Address Inputs Flash memory and PSRAM common Data Input/Outputs, Address Inputs or Command Inputs Power Supply for Flash memory Flash memory Power Supply for I/O Buffers Flash memory Optional Supply Voltage for Fast Program and Erase Ground PSRAM Power Supply Not Connected Internally Do Not Use as Internally Connected Flash memory and PSRAM Common Wait Data in Burst Mode Flash memory and PSRAM Latch Enable Input Flash memory and PSRAM Burst Clock
ADQ0-ADQ15 VDDF VDDQF VPPF VSS VDDP NC DU WAIT L K Flash Memory EF GF WF RPF WPF PSRAM EP GP WP CRP UBP LBP
Chip Enable Input Output Enable Input Write Enable Input Reset Input Write Protect Input
Chip Enable Input Output Enable Input Write Enable Input Configuration Register Enable Input Upper Byte Enable Input Lower Byte Enable Input
1. A16-A20 (in the case of a 32Mb PSRAM) or A16-A21 (in the case of a 64Mb PSRAM) are common to the Flash memory and the PSRAM 2. A21-A22 (if the MCP contains a 32Mb PSRAM) or A22 (if the MCP contains a 64Mb PSRAM) are Address Input(s) for the Flash memory component only.
8/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Figure 2. TFBGA connections (top view through package)
1 2 3 4 5 6
Summary description
7
8
A
DU
DU
DU
DU
B
NC
A18
A19
VSS
VDDF
NC
A21
NC
C
NC
LBP
NC
VSS
NC
K
A22
NC
D
NC
A17
NC
VPPF
WP
EP
NC
NC
E
NC
NC
NC
WPF
L
A20
NC
NC
F
NC
NC
UBP
RPF
WF
NC
NC
A16
G
NC
ADQ8
ADQ2
ADQ10
ADQ5
ADQ13
WAIT
NC
H
GP
ADQ0
ADQ1
ADQ3
ADQ12
ADQ14
ADQ7
NC
J
NC
GF
ADQ9
ADQ11
ADQ4
ADQ6
ADQ15
VDDQF
K
EF
DU
DU
NC
VDDP
NC
VDDQF
CRP
L
VSS
VSS
VDDQF
VDDF
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
Ai12017b
9/22
Signal descriptions
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (ADQ0-ADQ15 and A16-A22)
ADQ0-ADQ15 and A16-A20 (for the M36L0R7050U1/L1) or A16-A21 (for the M36L0R7060U1/L1) are common to the Flash memory and PSRAM components. In the Flash memory, the Address Inputs select the cells in the array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. In the PSRAM, the Address Inputs A16-A20 (/A21) are used in conjunction with ADQ0 to ADQ15, to select the cells in the memory array that are accessed during read and write operations.
2.2
Data Input/Output (ADQ0-ADQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation.
2.3
Latch Enable (L)
The Latch Enable input is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL for the Flash memory.
2.4
Clock (K)
The Clock input is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL for the Flash memory.
2.5
Wait (WAIT)
The Wait output is common to the Flash memory and PSRAM components. For details of how the WAIT signal behaves, please refer to the datasheets of the respective memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL for the Flash memory
10/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Signal descriptions
2.6
Flash memory Chip Enable (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. It is not allowed to set both EF and EP to VIL at the same time.
2.7
Flash memory Output Enable (GF)
The Output Enable input controls data outputs during the Bus Read operation of the Flash memory.
2.8
Flash memory Write Enable (WF)
The Write Enable input controls the Bus Write operation of the Flash memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.9
Flash memory Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to M58LRxxxGUL datasheet).
2.10
Flash memory Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58LRxxxGUL datasheet for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to the M58LRxxxGUL datasheet).
2.11
PSRAM Chip Enable (EP)
Chip Enable, EP, activates the device when driven Low (asserted). When de-asserted (VIH), the device is disabled and goes automatically in low-power Standby mode or Deep PowerDown mode, according to the RCR settings. It is not allowed to set both EF and EP to VIL at the same time.
11/22
Signal descriptions
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2.12
PSRAM Output Enable (GP)
When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the memory.
2.13
PSRAM Write Enable (WP)
Write Enable, WP, controls the Bus Write operation of the memory. When asserted (VIL), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array.
2.14
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the Upper Byte of the Address Inputs/ Data Inputs/Outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a write or read operation.
2.15
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte of the Address Inputs/Data Input/Outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write or read operation. If both LBP and UBP are disabled (High), the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low.
2.16
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19.
2.17
VDDF Flash memory Supply Voltage
VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase).
2.18
VCCP PSRAM Supply Voltage
The VCCP Supply Voltage is the core supply voltage.
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M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Signal descriptions
2.19
VDDQF Supply Voltage
VDDQF provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDDF. VDDQF can be tied to VDDF or can use a separate supply.
2.20
VPPF Flash memory Program Supply Voltage
VPPF is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPPF in the VPP1 range enables these functions (see the M58LRxxxGUL datasheet for the relevant values). VPPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed.
2.21
VSS Ground
VSS ground is the common Flash memory and PSRAM ground. It is the reference for the core supplies. It must be connected to the system ground.
2.22
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQF. VSSQ must be connected to VSS
Note:
Each device in a system should have VDDF, VDDQF and VPP decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
13/22
Functional description
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
3
Functional description
The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory and EP for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations on one of the Flash memory and the PSRAM components which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram
VDDF VPPF VDDQF A21-A22(1) or A22(2) EF WF RPF WPF GF 128 Mbit Flash Memory
K L A16-A20(1) or A16-A21(2) VCCP VSS
WAIT
ADQ0-ADQ15
EP GP WP CRP UBP LBP
AI12335
32 Mbit or 64 Mbit PSRAM
1. Address Inputs corresponding to the M36L0R7050U1 and M36L0R7050L1 devices. 2. Address Inputs corresponding to the M36L0R7060U1 and M36L0R7060L1 devices.
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M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Table 2. Operating modes - Standard Asynchronous operation
EF GF WF RPF VIL VIL VIH VIH VIL VIH VIL VIH VIH WAIT
(3)
Functional description
Operation(1) (2) Bus Read Flash memory Bus Write Output Disable Standby Reset Word Read Word Write
Other ADQ0L EP WP GP UBP LBP CRP A19 A18 Address ADQ7 Inputs VIH VIH VIL VIH X X VIH VIL VIL VIL VIL VIL VIH VIL VIL VIL \_/ Address In Valid Address In Valid 00(RCR) 10(BCR) X1(DIDR) VIH VIL VIH X X 0 or 00 (RCR) 1 or 10 (BCR)(6) VIL X X X X BCR/ RCR Data Any PSRAM mode is allowed. The PSRAM must be disabled.
ADQ8ADQ15
Data Output Data Input Address Input Hi-Z Hi-Z Hi-Z Address In/ Data Out Valid Address In/ Data In Valid Address In/ BCR, RCR or DIDR Content Valid
Address Latch VIL VIH X
VIL VIH VIH VIH VIH X X X X X VIH Hi-Z VIL Hi-Z
PSRAM
Read Configuration The Flash memory must Register (CR be disabled. controlled method)(4) Program Configuration Register (CR Controlled)(5) Output Disable/No Operation Deep PowerDown(7) Standby
VIH VIL VIL VIL VIL
X
VIL
Address In Valid
VIH X Any Flash memory mode is allowed. X VIH X VIH X X X
X
X
X
High-Z
X X
X X
X VIL
X X
X X
High-Z High-Z
1. The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode. 2. X = Don't Care 3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command. 4. Operating mode available in the M36L0R7060U1 and M36L0R7060L1 only (see M69KM096AA datasheet). 5. BCR and RCR only. 6. In the PSRAM of the M36L0R7050U1 and M36L0R7050L1, A19 is used to select between the BCR and the RCR whereas in the PSRAM of the M36L0R7060U1 and M36L0R7060L1 both A18 and A19 are used to select the BCR, the RCR or the DIDR. 7. The device enters Deep Power-Down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR set to `0'. The device remains in Deep Power-Down mode until E goes Low again and is held Low for tELEH(DP).
15/22
Maximum rating
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3.
Symbol TA TBIAS TSTG VIO
Absolute maximum ratings
Value Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage -25 -25 -55 -0.2 -0.2 -0.2 Max 85 85 125 2.45 2.45 10 100 100 C C C V V V mA hours Unit
VDDF, VDDQF Core and Input/Output Supply VCCP Voltages VPPF IO tVPPFH Flash Program Voltage Output Short Circuit Current Time for VPPF at VPPFH
16/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC measurement conditions
Flash memory Parameter Min VDDF Supply Voltage VCCP Supply Voltage VDDQF Supply Voltage VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Output Circuit Resistors (R1, R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VDDQF
VDDQF/2
PSRAM Unit Min - 1.7 - - - -25 30 16.7 Max - 1.95 - - - 85 V V V V V C pF k 2 0 to VCCP/2
VCCP/2
Max 1.95 - 1.95 9.5 VDDQF +0.4 85 30 16.7 5
1.7 - 1.7 8.5 -0.4 -25
ns V V
Figure 4.
AC measurement I/O waveform
VDDQF VDDQF/2 0V
AI06161b
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DC and AC parameters Figure 5.
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 AC measurement load circuit
VDDQF
VDDF
VDDQF R1 DEVICE UNDER TEST
0.1F 0.1F
CL
R2
CL includes JIG capacitance
AI08364c
Table 5.
Symbol CIN COUT
Device capacitance
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max(1) 14 18 Unit pF pF
1. Sampled only, not 100% tested.
Please refer to the M58LRxxxGUL and M69KM048AA or M69KM096AA datasheets for further DC and AC characteristics values and illustrations.
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M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Package mechanical
6
Package mechanical
Figure 6. TFBGA88 8 x 10mm, 8 x 10 ball array - 0.8mm pitch, bottom view package outline
D D1
e SE E E2 E1 b BALL "A1"
ddd FE FE1 A A1 FD SD A2
BGA-Z42
1. Drawing is not to scale.
Table 6.
Stacked TFBGA88 8 x 10mm - 8 x 10 active ball array, 0.8mm pitch, package data
millimeters inches Max 1.200 0.200 0.850 0.350 8.000 5.600 0.100 10.000 7.200 8.800 0.800 1.200 1.400 0.600 0.400 0.400 - - 9.900 10.100 0.3937 0.2835 0.3465 0.0315 0.0472 0.0551 0.0236 0.0157 0.0157 - - 0.3898 0.300 7.900 0.400 8.100 0.0335 0.0138 0.3150 0.2205 0.0039 0.3976 0.0118 0.3110 0.0157 0.3189 0.0079 Typ Min Max 0.0472
Symbol Typ A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE Min
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Part numbering
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
7
Part numbering
Table 7.
Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multi-Level, Multiple Bank, Burst Mode Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VDDP = VDDQF = 1.7V to 1.95V Flash 1 Density 7 = 128 Mbit Flash 2 Density 0 = No Die RAM 1 Density 5 = 32 Mbit 6 = 64 Mbit RAM 2 Density 0 = No Die Parameter Block Location U = Top Boot Block Flash L = Bottom Boot Block Flash Product Version 1 = 0.13m Flash technology and multilevel design, 85ns speeds; RAM, 70ns speed Mux I/O Package ZAM = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch Packing Option E = ECOPACK(R) Package, Standard Packing F = ECOPACK(R) Package, Tape & Reel Packing
Part numbering scheme
M36 L 0 R 7 0 5 0 L 1 ZAM F
Note:
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to '1'. For further information on any aspect of this device, please contact your nearest ST Sales Office.
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M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Revision history
8
Revision history
Table 8.
Date 08-Jun-2006
Document revision history
Revision 1 Initial release. Changes
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M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
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